Infineon HYB39S256400CT-7.5 Arkusz Danych Pobierz pdf

INFINEON Technologies 1 8.00

HYB39S256400/800/160CT(L)

256MBit Synchronous DRAM

256 MBit Synchronous DRAM

The HYB39S256400/800/160CT(L) are four bank Synchronous DRAM’s organized as 4 banks x

16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices

achieve high speed data transfer rates for CAS

-latencies by employing a chip architecture that

prefetches multiple bits and then synchronizes the output data to a system clock. The chip is

fabricated with INFINEON’s advanced 0.17 µm 256MBit DRAM process technology.

The device is designed to comply with all industry standards set for synchronous DRAM products,

both electrically and mechanically. All of the control, address, data input and output circuits are

synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur

at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible

depending on burst length, CAS

latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a

single 3.3V +/- 0.3V power supply and are available in TSOPII packages.

• High Performance:

• Fully Synchronous to Positive Clock Edge

• 0 to 70 °C operating temperature

• Four Banks controlled by BA0 & BA1

• Programmable CAS Latency: 2 & 3

• Programmable Wrap Sequence: Sequential

or Interleave

• Programmable Burst Length:

1, 2, 4, 8

• Full page burst length (optional) for

sequential wrap around

-7.5 -8 -8A Units

fCK 133 125 125 MHz

tCK3 7.5 8 8 ns

tAC3 5.4 6 6 ns

tCK2 10 10 12 ns

tAC2 6 6 6 ns

• Multiple Burst Read with Single Write

Operation

• Automatic and Controlled Precharge

Command

• Data Mask for Read / Write control (x4, x8)

• Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Power Down and Clock Suspend Mode

• 8192 refresh cycles / 64 ms (7,8 µs)

• Random Column Address every CLK

( 1-N Rule)

• Single 3.3V +/- 0.3V Power Supply

• LVTTL Interface versions

• Plastic Packages:

P-TSOPII-54 400mil width (x4, x8, x16)

• -7.5 parts for PC133 3-3-3 operation

-8 parts for PC100 2-2-2 operation

-8A parts for PC100 3-2-2 operation

1 2 3 4 5 6 ... 48 49

Podsumowanie treści

Strona 1 - 256 MBit Synchronous DRAM

INFINEON Technologies 1 8.00 HYB39S256400/800/160CT(L)

Strona 2 - Pin Description and Pinouts:

INFINEON Technologies 10 8.00 HYB39S256400/800/160CT(L)

Strona 3 - INFINEON Technologies 3 8.00

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Strona 4 - INFINEON Technologies 4 8.00

INFINEON Technologies 12 8.00 HYB39S256400/800/160CT(L)

Strona 5 - INFINEON Technologies 5 8.00

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Strona 6 - INFINEON Technologies 6 8.00

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Strona 7

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Strona 8

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Strona 9

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Strona 10 - Mode Register (Mx)

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Strona 11

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Strona 12

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Strona 13

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Strona 14

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 21Timing Diagrams1. Bank Activate Command Cycle2. Burst Read Operation3. Read

Strona 15

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 221. Bank Activate Command Cycle 2. Burst Read OperationRC"H" or &q

Strona 16

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 233. Read Interrupted by a Read 4. Read to Write Interval4.1 Read to Write In

Strona 17

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 244 2. Minimum Read to Write Interval4. 3. Non-Minimum Read to Write Interval

Strona 18

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 255. Burst Write Operation(Extra data is ignored aftertermination of a Burst.

Strona 19 - Notes for AC Parameters:

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 266. Write and Read Interrupt6.1 Write Interrupted by a Write6.2 Write Interr

Strona 20 - INFINEON Technologies 20 8.00

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 277. Burst Write and Read with Auto Precharge7.1 Burst Write with Auto-Precha

Strona 21 - Timing Diagrams

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 288. AC Parameters8.1 AC Parameters for a Write TimingAuto PrechargeBank BCom

Strona 22 - (CAS latency = 3)

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 298.2 AC Parameters for a Read TimingAC2Hi-ZDQActivateCo mma ndBank AReadBank

Strona 23 - INFINEON Technologies 23

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Strona 24 - INFINEON Technologies 24

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 309. Mode Register SetSet CommandMode RegisterAll BanksPrechargeCommandAnyCom

Strona 25 - 5. Burst Write Operation

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 3110. Power on Sequence and Auto Refresh (CBR)Inputs must be200stable forµsDQ

Strona 26 - 6. Write and Read Interrupt

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 3211. Clock Suspension ( Using CKE)11.1 Clock Suspension During Burst Read CA

Strona 27

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 3311.2 Clock Suspension During Burst Read CAS Latency = 3CSLDQMAddr.DQAPBSBan

Strona 28 - 8. AC Parameters

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 3411.3 Clock Suspension During Burst Write CAS Latency = 2Bank ADQMAddr.DQAPB

Strona 29 - INFINEON Technologies 29

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 3511.4 Clock Suspension During Burst Write CAS Latency = 3ClockSuspend2 Cycle

Strona 30 - 9. Mode Register Set

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 3612. Power Down Mode and Clock SuspendBSClock SuspendClock SuspendMode Entry

Strona 31 - INFINEON Technologies 31

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 3713. Self Refresh (Entry and Exit)BStSelf Refresh ExitCommand issuedAddr.DQM

Strona 32 - INFINEON Technologies 32

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 3814. Auto Refresh (CBR)(Minimum Interval)Addr.DQMDQAPBSAuto RefreshCommandAl

Strona 33 - INFINEON Technologies 33

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 3915. Random Column Read (Page within same Bank)15.1 CAS Latency = 2Ay1Addr.B

Strona 34 - INFINEON Technologies 34

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Strona 35 - INFINEON Technologies 35

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 4015.2 CAS Latency = 3Ay3CAwAddr.BSDQDQMAPZHiBank AActivateCommandReadCommand

Strona 36 - INFINEON Technologies 36

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 4116. Random Column write (Page within same Bank)16.1 CAS Latency = 2DBy 1Add

Strona 37 - INFINEON Technologies 37

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 4216.2. CAS Latency = 3CommandWriteBank BCBzDBw0Addr.BSDQDQMAPBank BActivateC

Strona 38 - 14. Auto Refresh (CBR)

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 4317. Random Row Read (Interleaving Banks) with Precharge17.1 CAS Latency = 2

Strona 39 - 15.1 CAS Latency = 2

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 4417.2 CAS Latency = 3ActivateCommandBank AAddr.DQMDQAPBSReadBank BCommandCom

Strona 40 - 15.2 CAS Latency = 3

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 4518. Random Row Write (Interleaving Banks) with Precharge18.1 CAS Latency =

Strona 41 - 16.1 CAS Latency = 2

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 4618.2 CAS Latency = 3DAx4Addr.DQMDQAPBSCommandBank ABank AActivateCommandHi-

Strona 42 - 16.2. CAS Latency = 3

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 4719. Precharge termination of a Burst19.1 CAS Latency = 2CommandActivateBank

Strona 43 - 17.1 CAS Latency = 2

HYB39S256400/800/160CT(L)256-MBit Synchronous DRAMINFINEON Technologies 48

Strona 44 - 17.2 CAS Latency = 3

INFINEON Technologies 21 8.00 HYB39S256400/800/160CT(L)

Strona 45 - 18.1 CAS Latency = 2

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Strona 46 - 18.2 CAS Latency = 3

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Strona 47 - 19.1 CAS Latency = 2

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Strona 48 - INFINEON Technologies 48

INFINEON Technologies 8 8.00 HYB39S256400/800/160CT(L)

Strona 49 - Change List

INFINEON Technologies 9 8.00 HYB39S256400/800/160CT(L)

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